1. Field of the Invention
The invention relates to a chip package, and, more specifically, to a chip package
2. Brief Description of the Related Art
In the recent years, the development of advanced technology is on the cutting edge. As a result, high-technology electronics manufacturing industries launch more feature-packed and humanized electronic products. These new products that hit the showroom are lighter, thinner, and smaller in design. In the manufacturing of these electronic products, the key component has to be the integrated circuit (IC) chip inside any electronic product.
The operability, performance, and life of an IC chip are greatly affected by its circuit design, wafer manufacturing, and chip packaging. For this present invention, the focus will be on a chip packaging technique. Since the features and speed of IC chips are increasing rapidly, the need for increasing the conductivity of the circuitry is necessary so that the signal delay and attenuation of the dies to the external circuitry are reduced. A chip package that allows good thermal dissipation and protection of the IC chips with a small overall dimension of the package is also necessary for higher performance chips. These are the goals to be achieved in chip packaging.
There are a vast variety of existing chip package techniques for mounting a die on a substrate. For a tape automated bonding (TAB) technique, traces on a tape help to fan out the routing. For a flip-chip technique, solder balls act as an interface for a die to electrically connect to an external circuit. For a wirebonding technique, bonded wires act as an interface for a die to electrically connect to an external circuit.
U.S. Pat. Nos. 6,673,698 and 6,800,941 and U.S. Pub. No. 2003/0122244, 2003/0122246 and 2003/0122243 teach another technology for packaging a chip comprising mounting a semiconductor chip, after being cut from a semiconductor wafer, on a substrate, and then forming a circuit over the chip and across the edge of the chip to the peripheral region outside the upper space over the chip.